Cypress Semiconductor /psoc63 /BLE /BLELL /PDU_ACCESS_ADDR_L_REGISTER

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Interpret as PDU_ACCESS_ADDR_L_REGISTER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PDU_ACCESS_ADDRESS_LOWER_BITS

Description

Access address (lower)

Fields

PDU_ACCESS_ADDRESS_LOWER_BITS

This field defines the lower 16 bits of the access address for each Link layer connection between any two devices.

Links

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